1. Field of Invention
The present invention relates generally to computer systems. More particularly, the present invention relates to a flow control circuit capable of dynamically detecting and avoiding obsolete data entry read operations in a First In First Out (FIFO) memory.
2. Related Art
Data transfer in most computer systems is typically conducted between a sending element and a receiving element according to a handshake protocol. In computer systems, data is often transmitted from the sending element at a higher rate than it can be consumed at the receiving element. In order to facilitate data communication between the sending element and the receiving element, high-speed buffers such as First In First Out (FIFO) devices are used.
A FIFO device typically comprises a plurality of serially arranged storage cells (or memory locations) which are sequentially written into and read from. A write address pointer holds the write binary address of the storage cell into which data will be written during the next write operation, and a read address pointer holds the read binary address of the storage cell from which data will be read during the next read operation.
FIG. 1 illustrates a conventional FIFO device 100. FIFO device 100 comprises a FIFO memory element 101, a write address circuit 103, a write multiplexer 105, a read address circuit 107, and a read multiplexer 109. Moreover, memory element 101 may be a Random Access Memory (RAM) in which reading and writing of data may be performed simultaneously and comprises a capacity of N words. While a read permission signal (RE) is asserted, data (RDATA) is read from an address designated by a read address (RADR) on a word-by-word basis at a clock timing of a clock signal (CLK). Similarly, while a write permission signal (WE) is asserted, data (WDATA) is written into an address designated by a write address (WADR) on a word-by-word basis at a clock timing of the clock signal CLK.
The read address circuit 107 receives the clock signal CLK and the read permission signal (RE). While the read permission signal (RE) is asserted, the read address circuit 107 increments the read address (RADR) by one at a clock timing of the clock signal CLK.
The write address circuit 103 receives the clock signal CLK and the write permission (WE). While the write permission signal (WE) is asserted, the write address circuit 103 increments the write address (WADR) by one at a clock timing of the clock signal CLK.
The conventional FIFO control circuit illustrated in FIG. 1 may be used to facilitate the data rate discrepancy between the sending element and the receiving element. However, such conventional FIFO control circuits do not detect or discard obsolete data stored in the FIFO memory, and therefore require additional read cycles to process obsolete data that need not be read.